1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of reading data from the same. More particularly, the present invention relates to a magnetic random access memory (MRAM) having a reference cell that is capable of maintaining a middle resistance between a high resistance and a low resistance of a magnetic tunneling junction (MTJ) layer according to changes in a resistance of the MTJ layer caused by an applied voltage and a method of reading data from the MRAM.
2. Description of the Related Art
A magnetic tunneling junction (MTJ) layer of a memory cell of an MRAM has a resistance that varies according to the direction of magnetization of a free magnetic film. When the direction of magnetization of the free magnetic film is the same as the direction of magnetization of a lower magnetic film formed under a tunneling film, the MTJ layer has a low resistance RL. When the direction of magnetization of the free magnetic film is not the same as the direction of magnetization of the lower magnetic film formed under the tunneling film, the MTJ layer has a high resistance RH. Hereinafter, the high resistance is referred to as a maximum resistance of the MTJ layer, and the low resistance is referred to as a minimum resistance of the MTJ layer.
An MRAM is a memory device that stores data “1” and “0” using the fact that the resistance of the MTJ layer is different according to the state of magnetization of the free magnetic film. Thus, in order to read information recorded in a memory cell, the MRAM includes a reference cell having a resistance (RH+RL)/2 (hereinafter, referred to as a middle resistance) that corresponds to an average resistance of the high resistance RH and the low resistance RL of the MTJ layer. The reference cell includes a transistor and an MTJ layer connected to the transistor. The middle resistance of the reference cell is the resistance of the MTJ layer provided in the reference cell.
During operation, the resistances RH and RL of the MTJ layer vary according to a voltage applied to the MTJ layer. Thus, as shown in FIG. 1, which is a graph of an ideal voltage versus resistance of a magnetic tunneling junction (MTJ) layer of a memory cell of an MRAM and an MTJ layer of a reference cell, the resistance of the MTJ layer of the reference cell of the MRAM, which is represented by a solid line, should be constant at a middle resistance (RH+RL)/2 between a low resistance RL (▪) and a high resistance RH (●) of the MTJ layer of the memory cell according to a voltage applied to the reference cell.
However, in a case of a reference cell of a conventional MRAM, the above-described conditions are not satisfied.
FIGS. 2, 5, and 7 are circuit diagrams of a memory cell and a reference cell of a conventional MRAM. FIG. 3 is a graph of voltage versus resistance of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 2. FIG. 4 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 2. FIG. 6 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 5.
For example, the reference cell of the conventional MRAM includes first through fourth MTJ layers 12, 14, 16, and 18 and a first transistor 10, as shown on the left side of a sensor amplifier (SA) in FIG. 2. A memory cell including a fifth MTJ layer 20 and a second transistor 24 is shown on the right side of the sensor amplifier SA in FIG. 2.
In such a device, a resistance is measured from an MTJ layer. Accordingly, in FIG. 2, each of the MTJ layers is indicated by a resistance. Hereinafter, MTJ layers in all circuits are indicated by a resistance.
The first and second MTJ layers 12 and 14 have a high resistance RH and a low resistance RL, respectively. The third and fourth MTJ layers 16 and 18 have a low resistance RL and a high resistance RH, respectively. The first and second MTJ layers 12 and 14 are connected in series to each other. The third and fourth MTJ layers 16 and 18 are also connected in series to each other. The first and second MTJ layers 12 and 14 and the third and fourth MTJ layers 16 and 18 are connected in parallel to each other. The first transistor 10 is connected between the second and fourth MTJ layers 14 and 18.
Referring to FIG. 2, a current Is is supplied to both the reference cell and the memory cell. VRef and VCell are a voltage measured in the reference cell and a voltage measured in the memory cell, respectively. A conventional MRAM including the reference cell and the memory cell shown in FIG. 2 reads information stored in the memory cell using a difference between the voltages VRef and VCell.
However, the current Is supplied to the reference cell from a current source is divided by two such that a current Is/2 is supplied to each of the first and second MTJ layers 12 and 14 and the third and fourth MTJ layers 16 and 18. As such, the voltage applied to each MTJ layer of the reference cell is about half of the voltage applied to the fifth MTJ layer 20 of the memory cell. For this reason, it is difficult to maintain the equivalent resistance of the reference cell at (RH+RL)/2, as shown in FIG. 3.
Since the equivalent resistance of the reference cell is not maintained at (RH+RL)/2, the voltage VRef measured in the reference cell has characteristics shown in FIG. 4.
More specifically, in FIG. 4, symbol ● is a graph showing a voltage VCell,H measured when the fifth MTJ layer 20 has a high resistance, symbol ▪ is a graph showing a voltage VCell,L measured when the fifth MTJ layer 20 has a low resistance, and a solid line is a graph showing a voltage VRef measured in the reference cell. Referring to the graphs in FIG. 4, the voltage VRef measured in the reference cell is different from (VCell, H+VCell,L)/2.
Since the voltage measured in the reference cell does not have a middle value between a maximum voltage and a minimum voltage measured in the memory cell, in a case of the conventional MRAM having the memory cell and the reference cell of FIG. 2, a sensing margin is reduced such that noise or malfunction may occur.
The reference cell and the memory cell of FIG. 5 are the same as the reference cell and the memory cell of FIG. 2 in constitution, but a voltage Vs instead of a current is applied to the reference cell and the memory cell. Thus, an MRAM having the reference cell and the memory cell of FIG. 5 reads information recorded in the memory cell using a difference between a current IRef measured in the reference cell and a current ICell measured in the memory cell. However, in the case of the MRAM of FIG. 5, like the MRAM of FIG. 2, voltages applied to each of the first through fourth MTJ layers 12, 14, 16, and 18 of the reference cell are about half of a voltage applied to the fifth MTJ layer 20 of the memory cell. Therefore, it is difficult to maintain the equivalent resistance of the reference cell at (RH+RL)/2, and it is also difficult to maintain the current IRef measured in the reference cell at a middle value (ICell,H+ICell,L)/2 between a maximum current ICell,H and a minimum current ICell,L measured in the memory cell.
Specifically, referring to FIG. 6, symbol ● is a graph showing maximum currents ICell,H measured in the memory cell, symbol ▪ is a graph showing minimum currents ICell,L measured in the memory cell, and a solid line is a graph showing a current IRef measured in the reference cell. Referring to the graphs in FIG. 6, the current IRef measured in the reference cell is very different from a middle value (ICell,H+ICell,L)/2 between the maximum currents ICell,H and the minimum currents ICell,L measured in the memory cell according to an applied voltage.
Thus, in case of the MRAM having the memory cell and the reference cell of FIG. 5, like the MRAM of FIG. 2, a sensing margin is reduced such that noise may occur.
FIG. 7 shows an MRAM having a reference cell including sixth and seventh MTJ layers 26 and 28, and the first transistor 10. The sixth MTJ layer 26 has a low resistance RL, and the seventh MTJ layer 28 has a resistance RH higher than the resistance of the sixth MTJ layer 26. The sixth and seventh MTJ layers 26 and 28 are connected in parallel to each other, and the first transistor 10 is connected between the sixth and seventh MTJ layers 26 and 28. Here, a voltage 0.5 Vs, which corresponds to ½ of a voltage Vs supplied to the memory cell, is applied to the reference cell.
In the MRAM shown in FIG. 7, like in the MRAM of FIG. 5, since the voltage 0.5Vs applied to the two MTJ layers 26 and 28 of the reference cell is about half of the voltage Vs applied to the fifth MTJ layer 20 of the memory cell, it is difficult to maintain the equivalent resistance of the reference cell at (RH+RL)/2. Thus, the current IRef measured in the reference cell of the MRAM of FIG. 7 cannot be maintained at a middle value (ICell,H+ICell,L)/2 between the maximum current ICell,H and the minimum current ICell,L measured in the memory cell, as shown in FIG. 6. For this reason, in the case of the MRAM of FIG. 7, a sensing margin is reduced such that noise or malfunction may occur.